Although the envelope detection is a widely used method in medical ultrasound (US) imaging to demodulate the amplitude of the received echo signal before any back-end processing, novel hardware-based approaches have been proposed for reducing its computational cost and complexity. In this paper, we present the modeling and FPGA implementation of an efficient envelope detector based on a Hilbert Transform (HT) approximation for US imaging applications. The proposed model exploits both the symmetry and the alternating zero-valued coefficients of a HT finite impulse response (FIR) filter to generate the in-phase and quadrature components that are necessary for the envelope computation. The hardware design was synthesized for a Stratix IV FPGA, by using the Simulink and the integrated DSP Builder toolbox, and implemented on a Terasic DE4-230 board. The accuracy of our algorithm was evaluated by the normalized root mean square error (NRMSE) cost function in comparison with the conventional method based on the absolute value of the discrete-time analytic signal via FFT. An excellent agreement was achieved between the theoretical simulations with the experimental result. The NRMSE was 0.42% and the overall FPGA utilization was less than 1.5%. Additionally, the proposed envelope detector is capable of generating envelope data at every FPGA clock cycle after 19 (0.48 µs) cycles of latency. The presented results corroborate the simplicity, flexibility and efficiency of our model for generating US envelope data in real-time, while reducing the hardware cost by up to 75% Ver menos