Please use this identifier to cite or link to this item: http://repositorio.unicamp.br/jspui/handle/REPOSIP/90790
Type: Artigo de evento
Title: Compressing Variable-length Instruction Traces
Author: Zinsly R.M.
Rigo S.
Borin E.
Abstract: Trace-driven simulation is a widely used technique to study computer architecture systems and to evaluate micro architecture features. A trace may contain execution information for billions or even trillions of instructions and storing these traces is a challenge itself. In this paper we describe VITC, a one-pass trace compression tool based in streams. VITC is based on SBC and compresses traces by exploiting the natural instruction and data redundancy in instruction streams. The VITC is capable of compressing traces of variable-length instructions, such as x86 instruction traces, and produces compressed files 87 times smaller than gzip and 47 times smaller than bzip2. The compressed traces produced by VITC are, on average, 1200 times smaller than the original ones. © 2012 IEEE.
Editor: 
Rights: fechado
Identifier DOI: 10.1109/WSCAD-SSC.2012.38
Address: http://www.scopus.com/inward/record.url?eid=2-s2.0-84872591618&partnerID=40&md5=46abd19240046711c898f60d8d037fbd
Date Issue: 2012
Appears in Collections:Unicamp - Artigos e Outros Documentos

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