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|Type:||Artigo de evento|
|Title:||Isdb-t Receiver Architecture And Vlsi Implementation In 65 Nm Cmos, For Fixed-reception High Definition Digital Television|
|Author:||De Lima E.R.|
|Abstract:||In this paper we present Architecture, Algorithms and VLSI implementation in CMOS 65 nm, of an ISDB-T Digital Receiver for Fixed-Reception of Digital Television. Furthermore, we show the System Test environment used to validate the FPGA and VLSI designs. The Receiver can work on Zero-IF or IF modes and several blocks are based on CORDIC Algorithm. It is the first VLSI implementation of an ISDB-T receiver in Brazil, in full compliance with the so-called ISDB-Tb. Furthermore, it is a landmark within IC-Brazil Program, which aims the development of an ecosystem in Microelectronics, capable of insert Brazil in the International Semiconductor landscape. © 2012 IEEE.|
|Appears in Collections:||Unicamp - Artigos e Outros Documentos|
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