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Type: Artigo de periódico
Title: Line And Point Tunneling In Scaled Si/sige Heterostructure Tfets
Author: Schmidt M.
Schafer A.
Minamisawa R.A.
Buca D.
Trellenkamp S.
Hartmann J.-M.
Zhao Q.-T.
Mantl S.
Abstract: In this letter, we systematically investigate the impact of gate length and channel orientation on the electrical performance of tunneling field-effect transistors (TFETs). We fabricate and characterize Si/SiGe heterostructure TFETs with p-doped compressively strained Si0.5Ge0.5 source, intrinsic Si channel, and n-doped Si drain. We observe a linear relation of gate length, Lg, and ON-current, ION, which is the first experimental proof of line tunneling occurring in a TFET. TCAD simulations support our observations. After forming gas annealing, short-channel TFETs exhibit different I-V characteristics compared with long-channel devices due to better passivation. © 2014 IEEE.
Editor: Institute of Electrical and Electronics Engineers Inc.
Rights: fechado
Identifier DOI: 10.1109/LED.2014.2320273
Date Issue: 2014
Appears in Collections:Unicamp - Artigos e Outros Documentos

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