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|Type:||Artigo de periódico|
|Title:||Roughness Analysis In Strained Silicon-on-insulator Wires And Films|
|Abstract:||Strained silicon is used to enhance performance in state-of-the-art CMOS. Under device operating conditions, the effect of strain is to reduce the carrier scattering at the channel by a smoother semiconductor surface. This has never been completely understood. This paper gives first evidence of the variation in surface roughness under realistic strained conditions. At the nanoscale, the SiO2/Si interface roughness is dependent on the scale of observation (self-affinity). To date, there is no experimental study of the SiO2/Si interface roughness scaling with strain. This work presents the effect of uniaxial and biaxial strains on the surface roughness of strained silicon-on-insulator films and wires using atomic force microscopy. Levels of strain ranging from 0% to 2.3%, encompassing those used in present CMOS devices have been investigated. It is shown that the silicon surface is affected by uniaxial and biaxial strains differently. Three surface roughness parameters have been analyzed: root mean square roughness, correlation length, and the Hurst exponent, which is used to describe the scaling behavior of a self-affine surface. The results show that the root mean square roughness decreases (up to ∼ 40%) with increasing tensile strain, whereas the correlation length increases (up to ∼ 63nm/%) with increasing tensile strain. The Hurst exponent also varies with strain and with the undulation wavelength regime (between ∼ 0.8 and 0.2). This dependency explains why some models used to determine the carrier mobility from experiments fit the data better with a Gaussian form, whereas other models fit the data better with an exponential form.|
|Editor:||American Institute of Physics Inc.|
|Appears in Collections:||Unicamp - Artigos e Outros Documentos|
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