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Type: Artigo de periódico
Title: Expression-tree-based algorithms for code compression on embedded RISC architectures
Author: Araujo, G
Centoducatte, P
Azevedo, R
Pannain, R
Abstract: Reducing program size has become an important goal in the design of modern embedded systems targeted to mass production. This problem has driven efforts aimed at designing processors with shorter instruction formats (e.g., ARM Thumb and MIPS16) or able to execute compressed code (e.g., IBM PowerPC 405), This paper proposes three code compression algorithms for embedded RISC architectures. In all algorithms, the encoded symbols are extracted from program expression trees. The algorithms differ on the granularity of the encoded symbol, which are selected from whole trees, parts of trees, or single instructions. Dictionary-based decompression engines are proposed for each compression algorithm. Experimental results, based on SPEC CINT95 programs running on the MIPS R4000 processor, reveal an average compression ratio of 53.6% (31.545) if the area of the decompression engine is (not) considered.
Subject: code compression
RISC architecture
Country: EUA
Editor: Ieee-inst Electrical Electronics Engineers Inc
Citation: Ieee Transactions On Very Large Scale Integration (vlsi) Systems. Ieee-inst Electrical Electronics Engineers Inc, v. 8, n. 5, n. 530, n. 533, 2000.
Rights: fechado
Identifier DOI: 10.1109/92.894158
Date Issue: 2000
Appears in Collections:Unicamp - Artigos e Outros Documentos

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