Please use this identifier to cite or link to this item: http://repositorio.unicamp.br/jspui/handle/REPOSIP/342904
Full metadata record
DC FieldValueLanguage
dc.contributor.CRUESPUNIVERSIDADE ESTADUAL DE CAMPINASpt_BR
dc.contributor.authorunicampNunes, Rafael Oliveira-
dc.contributor.authorunicampOrio, Roberto Lacerda de-
dc.typeArtigopt_BR
dc.titleEffect of lines and vias density on the BEOL temperature distributionpt_BR
dc.contributor.authorNunes, Rafael Oliveira-
dc.contributor.authorOrio, Roberto Lacerda de-
dc.subjectCondutividade térmicapt_BR
dc.subject.otherlanguageThermal conductivitypt_BR
dc.description.abstractA method to calculate the temperature distribution on the BEOL structure and its impact on the EM in a design environment has been developed and implemented. The study for a 45 nm technology indicated a large temperature variation from the local to the global interconnects, which should be considered for the EM induced resistance increase of the line, in contrast to the standard analysis through a fixed operation temperature throughout the BEOL. The results show that a significant additional temperature above 50°C exist on the layers M1 to M6 due the power dissipated from transistors. The temperature reduction on the local layer is evaluated increasing the number of vias and enlarging the interconnect lines, both with a direct influence on the BEOL thermal distribution. A reduction of 62.9°C is obtained for M1 layer, considering a fraction volume of 40% for lines and 6% for viaspt_BR
dc.relation.ispartofJournal of integrated circuits and systemspt_BR
dc.publisher.cityPorto Alegre, RSpt_BR
dc.publisher.countryBrasilpt_BR
dc.publisherSociedade Brasileira de Computaçãopt_BR
dc.date.issued2019-
dc.date.monthofcirculationAug.pt_BR
dc.language.isoengpt_BR
dc.description.volume14pt_BR
dc.description.issuenumber2pt_BR
dc.description.firstpage1pt_BR
dc.description.lastpage9pt_BR
dc.rightsFechadopt_BR
dc.sourceSCOPUSpt_BR
dc.identifier.issn1807-1953pt_BR
dc.identifier.eissn1872-0234pt_BR
dc.identifier.doi10.29292/jics.v14i2.63pt_BR
dc.identifier.urlhttp://ojs.fei.edu.br/ojs/index.php/JICS/article/view/63pt_BR
dc.description.sponsorshipCOORDENAÇÃO DE APERFEIÇOAMENTO DE PESSOAL DE NÍVEL SUPERIOR - CAPESpt_BR
dc.description.sponsordocumentnumber001pt_BR
dc.date.available2020-06-08T15:49:05Z-
dc.date.accessioned2020-06-08T15:49:05Z-
dc.description.provenanceSubmitted by Susilene Barbosa da Silva (susilene@unicamp.br) on 2020-06-08T15:49:05Z No. of bitstreams: 0. Added 1 bitstream(s) on 2020-09-03T11:55:59Z : No. of bitstreams: 1 2-s2.0-85074558004.pdf: 1724025 bytes, checksum: 6464e294a8a41762ca3f716b01e541db (MD5)en
dc.description.provenanceMade available in DSpace on 2020-06-08T15:49:05Z (GMT). No. of bitstreams: 0 Previous issue date: 2019en
dc.identifier.urihttp://repositorio.unicamp.br/jspui/handle/REPOSIP/342904-
dc.contributor.departmentSem informaçãopt_BR
dc.contributor.departmentDepartamento de Semicondutores, Instrumentos e Fotônicapt_BR
dc.contributor.unidadeFaculdade de Engenharia Elétrica e de Computaçãopt_BR
dc.contributor.unidadeFaculdade de Engenharia Elétrica e de Computaçãopt_BR
dc.subject.keywordBEOL temperaturept_BR
dc.subject.keywordChip reliabilitypt_BR
dc.identifier.source2-s2.0-85074558004pt_BR
dc.creator.orcidSem informaçãopt_BR
dc.creator.orcid0000-0002-9019-4835pt_BR
dc.type.formArtigopt_BR
Appears in Collections:FEEC - Artigos e Outros Documentos

Files in This Item:
File Description SizeFormat 
2-s2.0-85074558004.pdf1.68 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.