Analysis of vias position on the BEOL temperature distribution

Abstract

A study of the temperature distribution on the BEOL structure and its impact on the electromigration in a design environment has been developed and implemented. The study for a 45 nm technology indicated a large temperature variation from the local to the global interconnects, which should be considered for the EM-induced resistance increase of the line, in contrast to the standard analysis through a fixed operating temperature throughout the BEOL. The results show that a significant additional temperature above 30°C exists on the layers M1 to M11 due the power dissipated from transistors. The temperature reduction on the local layer is evaluated changing position and number of vias, both with a direct influence on the BEOL thermal distribution. The results show a reduction of temperature from 365 K to 358 K for M1 layer, considering a fraction volume of 6 % for vias distributed equally spaced with 2.4 μm.