Please use this identifier to cite or link to this item: http://repositorio.unicamp.br/jspui/handle/REPOSIP/341538
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dc.contributor.CRUESPUNIVERSIDADE ESTADUAL DE CAMPINASpt_BR
dc.identifier.isbn978-3-030-16053-1pt_BR
dc.contributor.authorunicampPinto Junior, Agord de Matos-
dc.contributor.authorunicampManera, Leandro Tiago-
dc.typeArtigopt_BR
dc.titlePhase-locked loop (PLL)-based frequency synthesizer for digital systems drivingpt_BR
dc.contributor.authorRaphael, R. N. S.-
dc.contributor.authorPinto Jr., Agord M.-
dc.contributor.authorManera, Leandro T.-
dc.contributor.authorFinco, Saulo-
dc.subjectSintetizadores de frequênciapt_BR
dc.subject.otherlanguageFrequency synthesizerspt_BR
dc.description.abstractThis work describes the implementation and operation features for a Phase-Locked Loop (PLL) architecture-based frequency synthesizer for clock generation and digital systems driving. From a programmable structure, considering an input reference frequency FREF = 50 MHz, schematic level simulation results indicate the possibility for generation of 3 distinct output frequencies, according to the transient response limits: TP (peak time) = 1.9 µs, TS (settling time) = 2 µs, and MP (maximum overshoot) <8%. The system was implemented through Cadence Virtuoso Analog Environment (ADE) from UMC CMOS technology (0.18 um), considering power supply VDD = 1.8 Vpt_BR
dc.relation.ispartofSmart innovation, systems and technologiespt_BR
dc.publisher.cityHeidelbergpt_BR
dc.publisher.countryAlemanhapt_BR
dc.publisherSpringerpt_BR
dc.date.issued2019-
dc.date.monthofcirculationMaypt_BR
dc.language.isoengpt_BR
dc.description.volume140pt_BR
dc.description.firstpage395pt_BR
dc.description.lastpage406pt_BR
dc.rightsFechadopt_BR
dc.sourceSCOPUSpt_BR
dc.identifier.issn2190-3018pt_BR
dc.identifier.eissn2190-3026pt_BR
dc.identifier.doi10.1007/978-3-030-16053-1_38pt_BR
dc.identifier.urlhttps://link.springer.com/chapter/10.1007/978-3-030-16053-1_38pt_BR
dc.date.available2020-05-15T17:56:09Z-
dc.date.accessioned2020-05-15T17:56:09Z-
dc.description.provenanceSubmitted by Susilene Barbosa da Silva (susilene@unicamp.br) on 2020-05-15T17:56:09Z No. of bitstreams: 0. Added 1 bitstream(s) on 2020-08-27T19:18:05Z : No. of bitstreams: 1 2-s2.0-85068621040.pdf: 714265 bytes, checksum: a57d029a6c0636322eb2f03a7904cff2 (MD5)en
dc.description.provenanceMade available in DSpace on 2020-05-15T17:56:09Z (GMT). No. of bitstreams: 0 Previous issue date: 2019en
dc.identifier.urihttp://repositorio.unicamp.br/jspui/handle/REPOSIP/341538-
dc.description.conferencenomeProceedings of the 4th Brazilian Technology Symposium (BTSym'18)pt_BR
dc.contributor.departmentSem informaçãopt_BR
dc.contributor.departmentDepartamento de Semicondutores, Instrumentos e Fotônicapt_BR
dc.contributor.unidadeFaculdade de Engenharia Elétrica e de Computaçãopt_BR
dc.contributor.unidadeFaculdade de Engenharia Elétrica e de Computaçãopt_BR
dc.subject.keywordFrequency synthesizerpt_BR
dc.subject.keywordPhase-locked looppt_BR
dc.subject.keywordThird-order systempt_BR
dc.subject.keywordDynamic modelingpt_BR
dc.identifier.source2-s2.0-85068621040pt_BR
dc.creator.orcid0000-0002-6458-934Xpt_BR
dc.creator.orcid0000-0002-8908-1470pt_BR
dc.type.formArtigo de eventopt_BR
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