Phase-locked loop (PLL)-based frequency synthesizer for digital systems driving

Abstract

This work describes the implementation and operation features for a Phase-Locked Loop (PLL) architecture-based frequency synthesizer for clock generation and digital systems driving. From a programmable structure, considering an input reference frequency FREF = 50 MHz, schematic level simulation results indicate the possibility for generation of 3 distinct output frequencies, according to the transient response limits: TP (peak time) = 1.9 µs, TS (settling time) = 2 µs, and MP (maximum overshoot) <8%. The system was implemented through Cadence Virtuoso Analog Environment (ADE) from UMC CMOS technology (0.18 um), considering power supply VDD = 1.8 V