Please use this identifier to cite or link to this item: http://repositorio.unicamp.br/jspui/handle/REPOSIP/341538
Type: Artigo
Title: Phase-locked loop (PLL)-based frequency synthesizer for digital systems driving
Author: Raphael, R. N. S.
Pinto Jr., Agord M.
Manera, Leandro T.
Finco, Saulo
Abstract: This work describes the implementation and operation features for a Phase-Locked Loop (PLL) architecture-based frequency synthesizer for clock generation and digital systems driving. From a programmable structure, considering an input reference frequency FREF = 50 MHz, schematic level simulation results indicate the possibility for generation of 3 distinct output frequencies, according to the transient response limits: TP (peak time) = 1.9 µs, TS (settling time) = 2 µs, and MP (maximum overshoot) <8%. The system was implemented through Cadence Virtuoso Analog Environment (ADE) from UMC CMOS technology (0.18 um), considering power supply VDD = 1.8 V
Subject: Sintetizadores de frequência
Country: Alemanha
Editor: Springer
Rights: Fechado
Identifier DOI: 10.1007/978-3-030-16053-1_38
Address: https://link.springer.com/chapter/10.1007/978-3-030-16053-1_38
Date Issue: 2019
Appears in Collections:FEEC - Artigos e Outros Documentos

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