Please use this identifier to cite or link to this item: http://repositorio.unicamp.br/jspui/handle/REPOSIP/327863
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dc.contributor.CRUESPUNIVERSIDADE DE ESTADUAL DE CAMPINASpt_BR
dc.identifier.isbn978-1-5090-2140-6pt
dc.contributor.authoremailjuan@ic.unicamp.br; amaral@cs.alberta.ca; guido@ic.unicamp.brpt_BR
dc.typeCongressopt_BR
dc.titleEvaluating And Improving Thread-level Speculation In Hardware Transactional Memoriesen
dc.contributor.authorSalamancapt_BR
dc.contributor.authorJuan; Amaralpt_BR
dc.contributor.authorJose Nelson; Araujopt_BR
dc.contributor.authorGuidopt_BR
unicamp.authorAraujo, Guido] Univ Estadual Campinas, Inst Comp, Campinas, SP, Brazilpt_BR
unicamp.author.external[Salamanca, Juanpt_BR
unicamp.author.external[Amaral, Jose Nelson] Univ Alberta, Dept Comp Sci, Edmonton, AB T6G 2M7, Canadapt_BR
dc.subjectHardware Transactional Memoryen
dc.subjectTransactional Memoryen
dc.subjectThread-level Speculationen
dc.description.abstractThis paper presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support for loop parallelization with Thread-Level Speculation (TLS). As a result it provides three contributions: (a) it shows that performance issues well-known to loop parallelism (e.g. false sharing) are exacerbated in the presence of HTM, and that capacity aborts can increase when one tries to overcome them; (b) it reveals that, although modern HTM extensions can provide support for TLS, they are not powerful enough to fully implement TLS; (c) it shows that simple code transformations, such as judicious strip mining and privatization techniques, can overcome such shortcomings, delivering speed-ups for programs that contain loop-carried dependencies. Experimental results reveal that, when these code transformations are used, speed-ups of up to 30% can be achieved for some loops for which previous research had reported slowdowns.en
dc.relation.ispartof2016 IEEE 30th International Parallel and Distributed Processing Symposium (IPDPS 2016)pt_BR
dc.publisherIEEEpt_BR
dc.publisherNew Yorkpt_BR
dc.date.issued2016pt_BR
dc.identifier.citation2016 Ieee 30th International Parallel And Distributed Processing Symposium (ipdps 2016). Ieee, p. 586 - 595, 2016.pt_BR
dc.language.isoEnglishpt_BR
dc.description.firstpage586pt_BR
dc.description.lastpage595pt_BR
dc.rightsfechadopt_BR
dc.sourceWOSpt_BR
dc.identifier.issn1530-2075pt_BR
dc.identifier.wosidWOS:000391251800061pt_BR
dc.identifier.doi10.1109/IPDPS.2016.84pt_BR
dc.identifier.urlhttp://ieeexplore.ieee.org/document/7516055/pt_BR
dc.date.available2017-11-13T13:22:19Z-
dc.date.accessioned2017-11-13T13:22:19Z-
dc.description.provenanceMade available in DSpace on 2017-11-13T13:22:19Z (GMT). No. of bitstreams: 1 000391251800061.pdf: 651943 bytes, checksum: 83b6e9b6351cf4aa3aca494450743c22 (MD5) Previous issue date: 2016en
dc.identifier.urihttp://repositorio.unicamp.br/jspui/handle/REPOSIP/327863-
dc.description.conferencenome30th IEEE International Parallel and Distributed Processing Symposium (IPDPS)pt_BR
dc.description.conferencedateMAY 23-27, 2016pt_BR
dc.description.conferencelocationIllinois Inst Technol, Chicago, ILpt_BR
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