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Type: Congresso
Title: Evaluating And Improving Thread-level Speculation In Hardware Transactional Memories
Author: Salamanca
Juan; Amaral
Jose Nelson; Araujo
Abstract: This paper presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support for loop parallelization with Thread-Level Speculation (TLS). As a result it provides three contributions: (a) it shows that performance issues well-known to loop parallelism (e.g. false sharing) are exacerbated in the presence of HTM, and that capacity aborts can increase when one tries to overcome them; (b) it reveals that, although modern HTM extensions can provide support for TLS, they are not powerful enough to fully implement TLS; (c) it shows that simple code transformations, such as judicious strip mining and privatization techniques, can overcome such shortcomings, delivering speed-ups for programs that contain loop-carried dependencies. Experimental results reveal that, when these code transformations are used, speed-ups of up to 30% can be achieved for some loops for which previous research had reported slowdowns.
Subject: Hardware Transactional Memory
Transactional Memory
Thread-level Speculation
Editor: IEEE
New York
Citation: 2016 Ieee 30th International Parallel And Distributed Processing Symposium (ipdps 2016). Ieee, p. 586 - 595, 2016.
Rights: fechado
Identifier DOI: 10.1109/IPDPS.2016.84
Date Issue: 2016
Appears in Collections:Unicamp - Artigos e Outros Documentos

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