Please use this identifier to cite or link to this item:
|Title:||Evaluating And Improving Thread-level Speculation In Hardware Transactional Memories|
Jose Nelson; Araujo
|Abstract:||This paper presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support for loop parallelization with Thread-Level Speculation (TLS). As a result it provides three contributions: (a) it shows that performance issues well-known to loop parallelism (e.g. false sharing) are exacerbated in the presence of HTM, and that capacity aborts can increase when one tries to overcome them; (b) it reveals that, although modern HTM extensions can provide support for TLS, they are not powerful enough to fully implement TLS; (c) it shows that simple code transformations, such as judicious strip mining and privatization techniques, can overcome such shortcomings, delivering speed-ups for programs that contain loop-carried dependencies. Experimental results reveal that, when these code transformations are used, speed-ups of up to 30% can be achieved for some loops for which previous research had reported slowdowns.|
|Subject:||Hardware Transactional Memory|
|Citation:||2016 Ieee 30th International Parallel And Distributed Processing Symposium (ipdps 2016). Ieee, p. 586 - 595, 2016.|
|Appears in Collections:||Unicamp - Artigos e Outros Documentos|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.