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|Type:||Artigo de evento|
|Title:||A New Circuit Topology For Lnas Using Partial Source Degeneration With Double Transistor Connection To Improve Gain And Input Impedance Matching Flexibility|
|Abstract:||One of the most important constraints that a designer must face in LNA design is the input impedance matching. The input impedance matching results in optimized gain and noise figure for the amplifier. Considering a single MOS transistor in common-source configuration, a degeneration of the source by an inductance Ls produces a desirable real part on the input impedance. Unfortunately, due to some technology restrains the designer must work with restringed options for Ls values limiting the capability to achieve a desirable impedance. The degeneration also introduces transconductance reduction due to the Ls voltage drop. A new topology is proposed to compensate this drawback by using two parallel transistors in CS configuration. The front most transistor has no inductance degeration while the other parallel transistor has the Ls degeneration. In so doing , the designer is able to imposes two different bias currents leading to a more refined adjustment of input impedance matching. Another advantage is to obtain a larger gain due to non-degenerated parcel. The same design strategy can be used with cascode connected LNAs using the same two parallel transistor in the CS configuration. In this paper we describe some design guidelines for the amplifier implementation. Very precise simulation including all RF parasitics for typical CMOS technology validates the new circuit configuration.|
|Appears in Collections:||Unicamp - Artigos e Outros Documentos|
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