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Type: Artigo de evento
Title: Dc Performance And Low Frequency Noise In N-mosfets Using Self-aligned Poly-si/sige Gate
Author: Jimenez H.G.
Manera L.T.
Teixeira R.C.
Rautemberg M.F.
Diniz J.A.
Doi I.
Tatsch P.J.
Figueroa H.E.
Swart J.W.
Abstract: The characterization of an n-MOS transistor with poly- Si/SiGe Gate fabricated with the CMOS process entirely developed in the Center for Semiconductor Components (CCS) at UNICAMP is presented. The Gate layer was grown by vertical LPCVD at 800 °C. The resultant transistor has a channel region with oxide thickness of 30 nm and self-aligned thick S/D region. The DC and Gm characteristics of poly-Si/SiGe n-MOS transistor are reported. The turn-on in the I-V characteristics increases and at a drain-tosource bias Vds of +0.1 V nMOSFETs with 3 μm gate length had peak transconductance (μS) increased as well, compared with conventional n-MOS with poly-Si gate. The Gm characteristics and low frequency noise 1/f of the n-MOS transistors are studied using devices sizes with width of 20 μm and several lengths. Promising devices for RF and microwave circuit applications, show low 1/f and high values of transconductance. © The Electrochemical Society.
Rights: fechado
Identifier DOI: 10.1149/1.2956027
Date Issue: 2008
Appears in Collections:Unicamp - Artigos e Outros Documentos

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