Please use this identifier to cite or link to this item:
Type: Artigo de evento
Title: A Precise Sample-and-hold Circuit Topology In Cmos For Low Voltage Applications With Offset Voltage Self Correction
Author: Ferreira L.H.C.
Moreno R.L.
Pimenta T.C.
Filho C.A.R.
Abstract: This work describes a new topology for CMOS sample-and-hold circuits in low voltage with self-correction of the offset voltage caused by mismatches in the differential input pair of the operational amplifier. The charge injection of the NMOS switches, although not properly modeled by the simulators, is an important factor and it is minimized in this topology. The results were obtained using the ACCUSiM II simulator on the AMS CMOS 0.8 μm CYE and they reveal the circuit has a reduced error of just 0.03% at the output. © 2002 IEEE.
Rights: fechado
Identifier DOI: 10.1109/ICECS.2002.1045329
Date Issue: 2002
Appears in Collections:Unicamp - Artigos e Outros Documentos

Files in This Item:
File Description SizeFormat 
2-s2.0-77956388536.pdf208.15 kBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.